Evolution of the semiconductor manufacturing industry is placing greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions continue to shrink, yet the industry needs to decrease time for achieving high-yield, high-value production. Minimizing the total time from detecting a yield problem to fixing it determines the return-on-investment for a semiconductor manufacturer.
Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a semiconductor wafer using a large number of fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a photoresist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer that are separated into individual semiconductor devices.
Inspection processes are used at various steps during semiconductor manufacturing to detect defects on wafers to promote higher yield in the manufacturing process and, thus, higher profits. Inspection has always been an important part of fabricating semiconductor devices such as integrated circuits (ICs). However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary because even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Certain defect identification algorithms used during inspection need an alignment target nearby to find a defect. Alignment targets are typically used to correctly place care areas and perform defect detection with sensitivity that depends on the care area. If the care area is placed slightly differently, then the defect inspection may suffer from lower sensitivity if the defect was in a lower sensitivity care area due to a shift in the care area.
Determining whether a defect identification algorithm can be accurate enough may be challenging. For example, the contrast on an image may be insufficient or design alignment targets may not be usable. Determining accuracy also can be problematic as inspection systems switch between wafers because while the two wafers may have the same design, the features formed on the wafers or the features in the images may be different between the two wafers.
Furthermore, many of nuisance filtering techniques rely on accurate alignment of the patch images to the design. Slight differences in the alignment quality (e.g., due to wafer-to-wafer variation or insufficient density of alignment targets) can cause either excursions or missed defects without any notification that insufficient alignment accuracy is the root cause. However, it can be difficult to determine if design-based alignment is not the root cause of defect density variation within one wafer or from wafer-to-wafer, which may be important for troubleshooting.
Two metrics are currently used. The first metric is a defect-based pattern to design alignment (PDA) quality. The distance between the detected defect and the closest alignment site is calculated. If the distance is small, the alignment score is high. If the distance is large, the alignment score is low. However, if no defects are detected on a certain section of a given wafer, it is unknown whether poor alignment is the reason for not detecting the defects.
The other metric is a swath-based PDA score. If there is a certain number of alignment targets per swath, the swath gets a passing score. Otherwise it gets a failing score. The swath-based PDA score has the disadvantage of not giving granular information. Entire regions within a swath may not be close to any alignment target and still receive a passing score. The opposite is also true. A swath could be reported as failing alignment but certain areas within that swath actually have enough alignment sites and defects can be detected correctly.
Therefore, an improved technique to determine alignment during semiconductor wafer inspection is needed.